Buses are generally classified as central processing unit (CPU) local buses or input/output (I/O) buses. Local buses are typically short in length, capable of transferring data at high speeds, and are matched to the memory system to maximize memory-CPU bandwidth. Usually, the designer of a Local bus is familiar with the types of devices that are to be connected to the bus and is able to design an efficient bus that is able to meet the needs of the devices. I/O buses, on the other hand, are often lengthy and may have many different types of devices connected to them. I/O buses also generally have a wide range in the data bandwidth of the devices connected to them.
I/O bus designs follow a bus standard because the number and variety of I/O devices are normally not fixed on a computer system. This permits users to add additional I/O devices to their system to meet their computing needs. As the interface to which these devices are connected, the I/O bus can be considered an expansion bus for adding I/O devices over time. Standards that let the computer designer and I/O device designer work independently, therefore, play a large role in determining the choice of bus that is implemented. As long as both the computer-system designer and the I/O device designer meet the requirements, any I/O device can connect to any computer.
Machines sometimes grow to be so popular that their I/O buses become de facto standards. An example of this is the well-known Industry Standard Architecture (ISA) bus structure. The ISA bus structure is implemented by many I/O device designers and is a desirable design choice for system designers because it supports a large share of peripheral devices. Unfortunately, since the ISA bus data throughput is limited to 8 MB/sec, a problem occurs when a user wants to connect a newer I/O device that runs at a throughput higher than 8 MB/sec to the ISA bus. An example of this problem is in the implementation of new Integrated Drive Electronics (IDE) drives in personal computers using the ISA bus structure.
In the past, when IDE drives operated with data throughputs of less than 8 MB/sec, a IDE drive attachment, know as an AT Attachment (ATA) bus, interfaced directly with the ISA bus. This connected the disk drive to the CPU through a local bus and a ISA I/O bus. Interfacing the ATA bus with the ISA bus was achieved by buffering the ISA data bus and the lower three bits of the address bus. Chip select signals were provided to the ATA bus by decoding the upper bits of the ISA address bus. This method of interface was inexpensive but limited in speed due to the inherent slow nature of the ISA bus and the buffers used to isolate the signals from the ISA bus. Because current ATA interfaces operate at data throughput rates in excess of 16.7 MB/sec, ATA buses are no longer connected to the system though the ISA bus. The data transfer requirements of the new drives are simply too high.
Today, IDE drive interfaces are designed for the high speed local bus, such as the VESA Local (VL) bus or Peripheral Component Interconnect (PCI). The fast data transfer requirements of the new drives can be met by connecting the ATA bus to the high speed local bus through an ATA to local bus bridge. Due to loading and protocol requirements of the ISA bus and the ATA bus, the ATA bus cannot be coupled to the high speed local bus by connecting it in series with the ISA bus. There are tight timing requirements on some ATA signals that require them to be directly driven by the local bus to ATA bridge. Similarly, there are tight timing requirement on some ISA signals that require them to be directly driven by the local bus to ISA bridge. Thus, in order to satisfy the loading and protocol requirements of the ISA bus and the ATA bus, designers have interfaced the ISA bus and the ATA bus directly in parallel with the high speed local bus by providing a dedicated pin on each bridge component for each signal to be transmitted to the ISA and ATA interfaces. When both the ISA bus and the ATA bus are connected directly in parallel to the high speed local bus, an additional bus bridge is utilized by designers for interfacing the ATA bus with the high speed local bus.
Using an additional bus bridge for directly interfacing the ATA bus to the Local bus requires an additional component package, additional pins for the package, and additional pin holes on the system circuit board. This translates to an additional cost to the system and the elimination of valuable real estate on the system circuit board. Since the prior art approach requires that every signal on the ISA and ATA interface be connected to a dedicated pin on the bridge component, the solution of packaging the two bridges into one physical component still requires an increase in the amount of pin and holes and thus does not completely solve the cost problem. Thus, there was little motivation in designing a combined ISA/ATA bridge component. Hence, circuitry which would allow a bridge component for the ISA and ATA interfaces to use a minimal amount of pins and packaging is desirable. As will be seen, the present invention overcomes the drawbacks of the prior art by providing circuitry which allows the output lines of a combined ISA/ATA bridge to be shared so that the number of pins on this single bridge component can be minimized. The present invention allows the pin requirement for a new combined ISA/ATA bridge, capable of highest speed ATA transfers, to be the same as previous ISA bridges.